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stpc ? consumer pc compatible embeded microprocessor 1/71 8/11/01 issue 2.4 figure 1. logic diagram n powerful x86 processor n 64-bit bus architecture n 64-bit dram controller n svga graphics controller n uma architecture n video scaler n digital pal/ntsc encoder n video input port n crt controller n 135mhz ramdac n 3 line flicker filter n scan converter n pci master / slave / arbiter ctrl n isa master/slave interface n ide controller n dma controller n interrupt controller n timer / counters n power management stpc consumer overview the stpc consumer integrates a standard 5th generation x86 core, a dram controller, a graph- ics subsystem, a video pipeline and support logic including pci, isa and ide controllers to provide a single consumer orientated pc compatible sub- system on a single device. the device is based on a tightly coupled unified memory architecture (uma), sharing the same memory array between the cpu main memory and the graphics and video frame buffers. extra facilities are implemented to handle video streams. features include smooth scaling and color space conversion of the video input stream and mixing with graphics data. the chip also in- cludes a built-in digital tv encoder and anti-flicker filters that allow stable, high-quality display on standard pal or ntsc television sets without ad- ditional components. the stpc consumer is packaged in a 388 plastic ball grid array (pbga). pbga388 x86 core host i/f dram ctrl vip pci m/s pci bus isa m/s eide pci m/s isa bus crtc hw cursor monitor tv output sync output color space converter color key chroma key video pipeline ccir input eide 2d svga antiflicker ipc digital pal/ ntsc s t p c c o n s u m e r obsolete product(s) - obsolete product(s)
stpc consumer 2/71 issue 2.4 - november 8, 2001 n x86 processor core n fully static 32-bit 5-stage pipeline, x86 processor fully pc compatible. n can access up to 4gbytes of external memory. n 8kbyte unified instruction and data cache with write back and write through capability. n parallel processing integral floating point unit, with automatic power down. n clock core speeds up to of 100 mhz. n fully static design for dynamic clock control. n low power and system management modes. n optimized design for 3.3v operation. n dram controller n integrated system memory and graphic frame memory. n supports up to 128 mbytes system memory in 4 banks and down to as little as 2mbytes. n supports 4mb, 8mb, 16mb, 32mb single- sided and double-sided dram simms. n four quad-word write buffers for cpu to dram and pci to dram cycles. n four 4-word read buffers for pci masters. n supports fast page mode & edo dram. n programmable timing for dram parameters including cas pulse width, cas pre-charge time and ras to cas delay. n 60, 70, 80 & 100ns dram speeds. n memory hole between 1 mbyte & 8 mbyte supported for pci/isa busses. n hidden refresh. to check if your memory device is supported by the stpc, please refer to table 6-24 in the programming manual. n graphics engine n 64-bit windows accelerator. n backward compatibility to svga standards. n hardware acceleration for text, bitblts, transparent blts and fills. n up to 64 x 64 bit graphics hardware cursor. n up to 4mb long linear frame buffer. n 8-, 16-, and 24-bit pixels. n drivers for windows and other operating systems. n vga controller n integrated 135mhz triple ramdac allowing for 1280 x 1024 x 75hz display. n requires external frequency synthesizer and reference sources. n 8-, 16-, 24-bit pixels. n interlaced or non-interlaced output. n video input port n accepts video inputs in ccir 601/656 or itu-r 601/656, and stream decoding. n optional 2:1 decimator n stores captured video in off setting area of the onboard frame buffer. n video pass through to the onboard pal/ ntsc encoder for full screen video images. n hsync and b/t generation or lock onto external video timing source. n video pipeline n two-tap interpolative horizontal filter. n two-tap interpolative vertical filter. n color space conversion (rgb to yuv and yuv to rgb). n programmable window size. n chroma and color keying for integrated video overlay. n programmable two tap filter with gamma correction or three tap flicker filter. n progressive to interlaced scan converter. n digital ntsc/pal encoder n n t s c - m , pa l - m ,pa l - b,d, g , h , i, pal -n e a s y programmable video outputs. n ccir601 encoding with programmable color subcarrier frequencies. n line skip/insert capability n interlaced or non-interlaced operation mode. n 625 lines/50hz or 525 lines/60hz 8 bit multiplexed cb-y-cr digital input. n cvbs and r,g,b simult aneous analog outputs through 10-bit dacs. n cross color reduction by specific trap filtering on luma within cvbs flow. n power down mode available on each dac. obsolete product(s) - obsolete product(s)
stpc consumer issue 2.4 - november 8, 2001 3/71 n pci controller n fully compliant with pci 2.1 specification. n integrated pci arbitration interface. up to 3 masters can connect directly. external pal allows for greater than 3 masters. n translation of pci cycles to isa bus. n translation of isa master initiated cycle to pci. n support for burst read/write from pci master. n 0.33x and 0.5x cpu clock pci clock. n isa master/slave interface n generates the isa clock from either 14.318mhz oscillator clock or pci clock n supports programmable extra wait state for isa cycles n supports i/o recovery time for back to back i/o cycles. n fast gate a20 and fast reset. n supports the single rom that c, d, or e. blocks shares with f block bios rom. n supports flash rom. n supports isa hidden refresh. n buffered dma & isa master cycles to reduce bandwidth utilization of the pci and host bus. nsp compliant. n ide interface n supports pio n supports up to mode 5 timings n transfer rates to 22 mbytes/sec n supports up to 4 ide devices n concurrent channel operation (pio modes) - 4 x 32-bit buffer fifos per channel n support for pio mode 3 & 4. n support for 11.1/16.6 mb/s, i/o channel ready pio data transfers. n individual drive timing for all four ide devices n supports both legacy & native ide modes n supports hard drives larger than 528mb n support for cd-rom and tape peripherals n backward compatibility with ide (ata-1). n drivers for windows and other operating systems n integrated peripheral controller n 2x8237/at compatible 7-channel dma controller. n 2x8259/at compatible interrupt controller. 16 interrupt inputs - isa and pci. n three 8254 compatible timer/counters. n co-processor error support logic. n power management n four power saving modes: on, doze, standby, suspend. n programmable system activity detector n supports smm and apm. n supports stopclk. n supports io trap & restart. n independent peripheral time-out timer to monitor hard disk, serial & parallel ports. n supports rtc, interrupts and dmas wake-up obsolete product(s) - obsolete product(s)
stpc consumer 4/71 issue 2.4 - november 8, 2001 obsolete product(s) - obsolete product(s)
general description issue 2.4 - november 8, 2001 5/71 1. general description at the heart of the stpc consumer is an ad- vanced processor block, dubbed the 5st86. the 5st86 includes a powerful x86 processor core along with a 64-bit dram controller, advanced 64bit accelerated graphics and video controller, a high speed pci local-bus controller and industry standard pc chip set functions (interrupt control- ler, dma controller, interval timer and isa bus) and eide controller. the stpc consumer has in addition to the 5st86, a video subsystem and high quality digital television output. the stmicroelectronics x86 processor core is em- bedded with standard and application specific pe- ripheral modules on the same silicon die. the core has all the functionality of the stmicroelectronics standard x86 processor products, including the low power system management mode (smm). system management mode (smm) provides an additional interrupt and address space that can be used for system power management or software transparent emulation of peripherals. while run- ning in isolated smm address space, the smm in- terrupt routine can execute without interfering with the operating system or application programs. further power management facilities include a suspend mode that can be initiated from either hardware or software. because of the static nature of the core, no internal data is lost. the stpc consumer makes use of a tightly cou- pled unified memory architecture (uma), where the same memory array is used for cpu main memory and graphics frame-buffer. this signifi- cantly reduces total system memory with system performances equal to that of a comparable solu- tion with separate frame buffer and system mem- ory. in addition, memory bandwidth is improved by attaching the graphics engine directly to the 64-bit processor host interface running at the speed of the processor bus rather than the traditional pci bus. the 64-bit wide memory array provides the sys- tem with 320mb/s peak bandwidth, double that of an equivalent system using 32 bits. this allows for higher screen resolutions and greater color depth. the processor bus runs at the speed of the proc- essor (dx devices) or half the speed (dx2 devic- es). the standard pc chipset functions (dma, inter- rupt controller, timers, power management logic) are integrated with the x86 processor core. the pci bus is the main data communication link to the stpc consumer chip. the stpc consum- er translates appropriate host bus i/o and memory cycles onto the pci bus. it also supports the gen- eration of configuration cycles on the pci bus. the stpc consumer, as a pci bus agent (host bridge class), fully complies with pci specification 2.1. the chip-set also implements the pci manda- tory header registers in type 0 pci configuration space for easy porting of pci aware system bi- os. the device contains a pci arbitration function for three external pci devices. the stpc consumer integrates an isa bus con- troller. peripheral modules such as parallel and serial communications ports, keyboard controllers and additional isa devices can be accessed by the stpc consumer chip set through this bus. an industry standard eide (ata 2) controller is built in to the stpc consumer and connected in- ternally via the pci bus. graphics functions are controlled by the on-chip svga controller and the monitor display is man- aged by the 2d graphics display engine. this graphics engine is tuned to work with the host cpu to provide a balanced graphics system with a low silicon area cost. it performs limited graphics drawing operations, which include hard- ware acceleration of text, bitblts, transparent blts and fills. these operations can act on off-screen or on-screen areas. the frame buffer size ranges up to 4 mbytes anywhere in the physical main memory. the graphics resolution supported is a maximum of 1280x1024 in 65536 colours at 75hz refresh rate and is vga and svga compatible. horizontal timing fields are vga compatible while the vertical fields are extended by one bit to accommodate the above display resolution. stpc consumer provides several additional func- tions to handle mpeg or similar video streams. the video input port accepts an encoded digital video stream in one of a number of industry stand- ard formats, decodes it, optionally decimates it by a factor of 2:1, and deposits it into an off screen area of the frame buffer. an interrupt request can be generated when an entire field or frame has been captured. obsolete product(s) - obsolete product(s)
general description 6/71 issue 2.4 - november 8, 2001 the video output pipeline incorporates a video- scaler and color space converter function and pro- visions in the crt controller to display a video window. while repainting the screen the crt con- troller fetches both the video as well as the normal non-video frame buffer in two separate internal fifos (256-bytes each). the video stream can be color-space converted (optionally) and smooth scaled. smooth interpolative scaling in both hori- zontal and vertical directions are implemented. color and chroma key functions are also imple- mented to allow mixing video stream with non-vid- eo frame buffer. the video output passes directly to the ramdac for monitor output or through another optional color space converter (rgb to 4:2:2 ycrcb) to the programmable anti-flicker filter. the flicker filter is configured as either a two line filter with gamma correction (primarily designed for dos type text) or a 3 line flicker filter (primarily designed for win- dows type displays). the flicker filter is optional and can be software disabled for use with video on large screen areas. the video output pipeline of the stpc consumer interfaces directly to the internal digital tv encod- er. it takes a 24 bit rgb non-interlaced pixel stream and converts to a multiplexed 4:2:2 ycrcb 8 bit output stream, the logic includes a progres- sive to interlaced scan converter and logic to in- sert appropriate ccir656 timing reference codes into the output stream. it facilitates the high quality display of vga or full screen video streams re- ceived via the video input port to standard ntsc or pal televisions. the stpc consumer core is compliant with the advanced power management (apm) specifica- tion to provide a standard method by which the bios can control the power used by personal computers. the power management unit module (pmu) controls the power consumption by provid- ing a comprehensive set of features that control the power usage and supports compliance with the united states environmental protection agen- cy's energy star computer program. the pmu provides following hardware structures to assist the software in managing the power consumption by the system. - system activity detection. - 3 power-down timers detecting system inactivity: - doze timer (short durations). - stand-by timer (medium durations). - suspend timer (long durations). - house-keeping activity detection. - house-keeping timer to cope with short bursts of house-keeping activity while dozing or in stand-by state. - peripheral activity detection. - peripheral timer detecting peripheral inactivity - susp# modulation to adjust the system perform- ance in various power down states of the system including full power on state. - power control outputs to disable power from dif- ferent planes of the board. lack of system activity for progressively longer period of times is detected by the three power down timers. these timers can generate smi in- terrupts to cpu so that the smm software can put the system in decreasing states of power con- sumption. alternatively, system activity in a power down state can generate smi interrupt to allow the software to bring the system back up to full power on state. the chip-set supports up to three power down states: doze state, stand-by state and sus- pend mode. these correspond to decreasing lev- els of power savings. power down puts the stpc consumer into sus- pend mode. the processor completes execution of the current instruction, any pending decoded in- structions and associated bus cycles. during the suspend mode, internal clocks are stopped. re- moving power down, the processor resumes in- struction fetching and begins execution in the in- struction stream at the point it had stopped. a reference design for the stpc consumer is available including the schematics and layout files, the design is a pc atx motherboard design. the design is available as a demonstration board for application and system development. the stpc consumer is supported by several bios vendors, including the super i/o device used in the reference design. drivers for 2d accel- erator, video features and eide are availaible on various operating systems. the stpc consumer has been designed using modern reusable modular design techniques, it is possible to add or remove the standard features of the stpc consumer or other variants of the 5st86 family. contact your local stmicroelecton- ics sales office for further information. obsolete product(s) - obsolete product(s)
general description issue 2.4 - november 8, 2001 7/71 figure 1-1 functionnal description x86 core host i/f dram i/f 2d svga vip pci m/s pci bus isa m/s eide pci m/s isa bus crtc hw cursor monitor tv output sync output ipc 82c206 anti-flicker color space converter color key chroma key video pipeline ccir input eide digital pal/ ntsc obsolete product(s) - obsolete product(s)
general description 8/71 issue 2.4 - november 8, 2001 figure 1-2 typical application stpc consumer isa pci 4x 16-bit edo drams super i/o 2x eide flash keyboard / mouse serial ports parallel port floppy monitor tv video svga ccir601 ccir656 s-vhs rgb pal ntsc irq dma.req dma.ack dmux dmux mux mux rtc obsolete product(s) - obsolete product(s)
pin description issue 2.4 - november 8, 2001 9/71 2. pin description 2.1 introduction the stpc consumer integrates most of the func- tionalities of the pc architecture. as a result, many of the traditional interconnections between the host pc microprocessor and the peripheral devic- es are totally internal to the stpc consumer. this offers improved performance due to the tight cou- pling of the processor core and these peripherals. as a result many of the external pin connections are made directly to the on-chip peripheral func- tions. fi g ure 2-1 shows the stpc consumers external interfaces. it defines the main busses and their function. table 2-1 describes the physical imple- mentation listing signal types and their functionali- ties. tabl e 2-2 provides a full pin listing and de- scription. tabl e 2-3 provides a full listing of the stpc consumer pin locations of package by physical connection. please refer to the pin alloca- tion drawing for reference. note: several interface pins are multiplexed with other functions, refer to the pin description sec- tion for further details table 2-1. signal description group name qty basic clocks reset & xtal(sys) 12 dram controller 89 pci interface (pci) 58 isa / ide / ipc combined interface 88 video input (vip) 9 tv output 10 vga monitor interface 10 grounds 69 v dd 26 analog specific v cc /v dd 12 reserved 5 total pin count 388 figure 2-1. stpc consumer external interfaces south north pci x86 dram vga vip tv sys isa/ide ipc 89 10 9 10 58 13 77 11 stpc consumer obsolete product(s) - obsolete product(s)
pin description 10/71 issue 2.4 - november 8, 2001 table 2-2. definition of signal pins signal name dir description qty basic clocks and resets sysrsti# i system reset / power good 1 xtali i 14.3mhz crystal input 1 xtalo i/o 14.3mhz crystal output - external oscillator input 1 hclk o host clock (test) 1 dev_clk o 24mhz peripheral clock (floppy drive) 1 gclk2x i/o 80mhz graphics clock 1 dclk i/o 135mhz dot clock 1 pci_clki i 33mhz pci input clock 1 pci_clko o 33mhz pci output clock (from internal pll) 1 sysrsto# o reset output to system 1 isa_clk o isa clock output - multiplexer select line for ipc 1 isa_clk2x o isa clock x 2 output - multiplexer select line for ipc 1 memory interface ma[11:0] o memory address 12 ras#[3:0] o row address strobe 4 cas#[7:0] o column address strobe 8 mwe# o write enable 1 md[63:0] i/o memory data 64 pci interface ad[31:0] i/o pci address / data 32 cbe[3:0] i/o bus commands / byte enables 4 frame# i/o cycle frame 1 trdy# i/o target ready 1 irdy# i/o initiator ready 1 stop# i/o stop transaction 1 devsel# i/o device select 1 par i/o parity signal transactions 1 serr# o system error 1 lock# i pci lock 1 pcireq#[2:0] i pci request 3 pcignt#[2:0] o pci grant 3 pci_int[3:0] i pci interrupt request 4 vdd5 i 5v power supply for pci esd protection 4 isa and ide combined address/data la[23:22] / scs3#,scs1# i/o unlatched address (isa) / secondary chip select (ide) 2 la[21:20] / pcs3#,pcs1# i/o unlatched address (isa) / primary chip select (ide) 2 la[19:17] / da[2:0] o unlatched address (isa) / address (ide) 3 rmrtccs# / dd[15] i/o rom/rtc chip select / data bus bit 15 (ide) 1 kbcs# / dd[14] i/o keyboard chip select / data bus bit 14 (ide) 1 rtcrw# / dd[13] i/o rtc read/write / data bus bit 13 (ide) 1 rtcds# / dd[12] i/o rtc data strobe / data bus bit 12 (ide) 1 sa[19:8] / dd[11:0] i/o latched address (isa) / data bus (ide) 16 sa[7:0] i/o latched address (ide) 4 sd[15:0] i/o data bus (isa) 16 obsolete product(s) - obsolete product(s)
pin description issue 2.4 - november 8, 2001 11/71 isa/ide combined control iochrdy / diordy i/o i/o channel ready (isa) - busy/ready (ide) 1 isa control osc14m o isa bus synchronisation clock 1 ale o address latch enable 1 bhe# i/o system bus high enable 1 memr#, memw# i/o memory read and memory write 2 smemr#, smemw# o system memory read and memory write 2 ior#, iow# i/o i/o read and write 2 master# i add on card owns bus 1 mcs16#, iocs16# i memory/io chip select16 2 ref# o refresh cycle. 1 aen o address enable 1 zws# i zero wait state 1 iochck# i i/o channel check. 1 isaoe# o bidirectional oe control 1 rtcas o real time clock address strobe 1 gpiocs# i/o general purpose chip select 1 ide control pirq i primary interrupt request 1 sirq i secondary interrupt request 1 pdrq i primary dma request 1 sdrq i secondary dma request 1 pdack# o primary dma acknowledge 1 sdack# o secondary dma acknowledge 1 pior# i/o primary i/o read 1 piow# o primary i/o write 1 sior# i/o secondary i/o read 1 siow# o secondary i/o write 1 ipc irq_mux[3:0] i multiplexed interrupt request 4 dreq_mux[1:0] i multiplexed dma request 2 dack_enc[2:0] o dma acknowledge 3 tc o isa terminal count 1 monitor interface red, green, blue o red, green, blue 3 vsync o vertical sync 1 hsync o horizontal sync 1 vref_dac i dac voltage reference 1 rset i resistor set 1 comp i compensation 1 col_sel o colour select 1 scl / ddc[1] i/o i2c interface - clock / can be used for vga ddc[1] signal 1 sda / ddc[0] i/o i2c interface - data / can be used for vga ddc[0] signal 1 table 2-2. definition of signal pins signal name dir description qty obsolete product(s) - obsolete product(s)
pin description 12/71 issue 2.4 - november 8, 2001 video input vclk i pixel clock 1 vin i yuv video data input ccir 601 or 656 8 tv output red_tv, green_tv, blue_tv o analog video outputs synchronized with cvbs 3 vcs o composite synch or horizontal line sync output 1 odd_even o frame synchronisation 1 cvbs o analog video composite output (luminance / chrominance) 1 iref1_tv i reference current of 9bit dac for cvbs 1 vref1_tv i reference voltage of 9bit dac for cvbs 1 iref2_tv i reference current of 8bit dac for r,g,b 1 vref2_tv i reference voltage of 8bit dac for r,g,b 1 vssa_tv i analog vss for dac 1 vdda_tv i analog vdd for dac 1 miscellaneous spkrd o speaker device output 1 scan_enable i reserved (test pin) 1 table 2-2. definition of signal pins signal name dir description qty obsolete product(s) - obsolete product(s)
pin description issue 2.4 - november 8, 2001 13/71 2.2 signal descriptions 2.2.1 basic clocks and resets sysrsti system reset/power good. this input is low when the reset switch is depressed. other- wise, it reflects the power supplys power good signal. sysrsti is asynchronous to all clocks, and acts as a negative active reset. the reset cir- cuit initiates a hard reset on the rising edge of sysrsti. sysrsto# reset output to system. this is the system reset signal and is used to reset the rest of the components (not on host bus) in the system. the isa bus reset is an externally inverted buff- ered version of this output and the pci bus reset is an externally buffered version of this output. xtali 14.3mhz crystal input xtalo 14.3mhz crystal output. these pins are the 14.318 mhz crystal input; this clock is used as the reference clock for the internal frequency syn- thesizer to generate the hclk, clk24m, gclk2x and dclk clocks. a 14.318 mhz series cut quartz crystal should be connected between these two pins. balance capacitors of 15 pf should also be added. in the event of an external oscillator providing the master clock signal to the stpc consumer device, the ttl signal should be provided on xtalo. hclk host clock. this is the host 1x clock. its frequency can vary from 25 to 75 mhz. all host transactions and pci transactions are synchro- nized to this clock. the dram controller to exe- cute the host transactions is also driven by this clock. in normal mode, this output clock is gener- ated by the internal pll. gclk2x 80mhz graphics clock. this is the graphics 2x clock, which drives the graphics en- gine and the dram controller to execute the graphics and display cycles. normally gclk2x is generated by the internal fre- quency synthesizer, and this pin is an output. by setting a bit in strap register 2, this pin can be made an input so that an external clock can re- place the internal frequency synthesizer. pci_clki 33mhz pci input clock this signal is the pci bus clock input and should be driven from the pci_clko pin. pci_clko 33mhz pci output clock. this is the master pci bus clock output. dclk 135mhz dot clock. this is the dot clock, which drives graphics display cycles. its frequency can go from 8mhz (using internal pll) up to 135 mhz, and it is required to have a worst case duty cycle of 60-40. this signal is either driven by the internal pll (vga) or an external 27mhz oscillator (when the com- posite video output is enabled). the direction can be controlled by a strap option or an internal regis- ter bit. isa_clk isa clock output (also multiplexer se- lect line for ipc). this pin produces the clock signal for the isa bus. it is also used with isa_clk2x as the multiplexor control lines for the interrupt controller interrupt input lines. this is a divided down version of either the pciclk or osc14m. isa_clkx2 isa clock output (also multiplexer select line for ipc). this pin produces a signal that is twice the frequency of the isa bus clock signal. it is also used with isa_clk as the multi- plexor control lines for the interrupt controller in- put lines. dev_clk 24mhz peripheral clock output. this 24mhz signal is provided as a convenience for the system integration of a floppy disk driver function in an external chip. osc14m isa bus synchronisation clock output. this is the buffered 14.318 mhz clock to the isa bus. 2.2.2 memory interface ma[11:0] memory address output. these 12 mul- tiplexed memory address pins support external dram with up to 4k refresh. these include all 16m x n and some 4m x n dram modules. the address signals must be externally buffered to support more than 16 dram chips. the timing of these signals can be adjusted by software to match the timings of most dram modules. obsolete product(s) - obsolete product(s)
pin description 14/71 issue 2.4 - november 8, 2001 md[63:0] memory data i/o. this is the 64-bit memory data bus. if only half of a bank is populat- ed, md63-32 is pulled high, data is on md31-0. md[40-0] are read by the device strap option reg- isters during rising edge of sysrsti. ras#[3:0] row address strobe output. there are 4 active low row address strobe outputs, one for each bank of the memory. each bank contains 4 or 8-bytes of data. the memory controller allows half of a bank (4-bytes) to be populated to enable memory upgrade at finer granularity. the ras# signals drive the simms directly with- out any external buffering. these pins are always outputs, but they can also simultaneously be in- puts, to allow the memory controller to monitor the value of the ras# signals at the pins. cas#[7:0] column address strobe output. there are 8 active low column address strobe outputs, one each for each byte of the memory. the cas# signals drive the simms either directly or through external buffers. these pins are always outputs, but they can also simultaneously be inputs, to allow the memory controller to monitor the value of the cas# signals at the pins. mwe# write enable output. write enable speci- fies whether the memory access is a read (mwe# = h) or a write (mwe# = l). this single write ena- ble controls all the dram. it can be externally buffered to boost the maximum number of loads (dram chips) supported. the mwe# signals drive the simms directly with- out any external buffering. 2.2.3 video interface vclk pixel clock input. vin[7:0] yuv video data input ccir 601 or 656. time multiplexed 4:2:2 luminance and chromi- nance data as defined in itu-r rec601-2 and rec656 (except for ttl input levels). this bus in- terfaces with an mpeg video decoder output port and typically carries a stream of cb,y,cr,y digital video at vclk frequency, clocked on the rising edge (by default) of vclk. a 54-mbit/s double cb, y, cr, y input multiplex is supported for double encoding application (rising and falling edge of ckref are operating). 2.2.4 tv output red_tv / c_tv analog video outputs synchro- nized with cvbs. this output is current-driven and must be connected to analog ground over a load resistor (r load ). following the load resistor, a simple analog low pass filter is recommended. in s-vhs mode, this is the chrominance output. green_tv / y_tv analog video outputs syn- chronized with cvbs. this output is current-driv- en and must be connected to analog ground over a load resistor (r load ). following the load resis- tor, a simple analog low pass filter is recommend- ed. in s-vhs mode, this is the luminance output. blue_tv / cvbs analog video outputs synchro- nized with cvbs. this output is current-driven and must be connected to analog ground over a load resistor (r load ). following the load resistor, a simple analog low pass filter is recommended. in s-vhs mode, this is a second composite output. vcs line synchronisation output. this pin is an input in oddev+hsync or vsync + hsync or vsync slave modes and an output in all other modes (master/slave) the signal is synchronous to rising edge of ck- ref. the default polarity uses a negative pulse odd_even frame synchronisation ourput. this pin supports the frame synchronisation signal. it is an input in slave modes, except when sync is extracted from ycrcb data, and an output in mas- ter mode and when sync is extracted from ycrcb data the signal is synchronous to rising edge of dclk. the default polarity for this pin is: - odd (not-top) field : low level - even (bottom) field : high level iref1_tv ref. current for cvbs 10-bit dac. vref1_tv ref. voltage for cvbs 10-bit dac. iref2_tv reference current for rgb 9-bit dac. vref2_tv reference voltage for rgb 9-bit dac. vssa_tv analog v ss for dac vdda_tv analog v dd for dac obsolete product(s) - obsolete product(s)
pin description issue 2.4 - november 8, 2001 15/71 cvbs analog video composite output (luminance/ chrominance). cvbs is current-driven and must be connected to analog ground over a load resis- tor (r load ). following the load resistor, a simple analog low pass filter is recommended. 2.2.5 pci interface ad[31:0] pci address/data. this is the 32-bit multiplexed address and data bus of the pci. this bus is driven by the master during the address phase and data phase of write transactions. it is driven by the target during data phase of read transactions. cbe#[3:0] bus commands/byte enables. these are the multiplexed command and byte enable signals of the pci bus. during the address phase they define the command and during the data phase they carry the byte enable information. these pins are inputs when a pci master other than the stpc consumer owns the bus and out- puts when the stpc consumer owns the bus. frame# cycle frame. this is the frame signal of the pci bus. it is an input when a pci master owns the bus and is an output when stpc consumer owns the pci bus. trdy# target ready. this is the target ready sig- nal of the pci bus. it is driven as an output when the stpc consumer is the target of the current bus transaction. it is used as an input when stpc consumer initiates a cycle on the pci bus. irdy# initiator ready. this is the initiator ready signal of the pci bus. it is used as an output when the stpc consumer initiates a bus cycle on the pci bus. it is used as an input during the pci cy- cles targeted to the stpc consumer to determine when the current pci master is ready to complete the current transaction. stop# stop transaction. stop is used to imple- ment the disconnect, retry and abort protocol of the pci bus. it is used as an input for the bus cy- cles initiated by the stpc consumer and is used as an output when a pci master cycle is targeted to the stpc consumer. devsel# i/o device select. this signal is used as an input when the stpc consumer initiates a bus cycle on the pci bus to determine if a pci slave device has decoded itself to be the target of the current transaction. it is asserted as an output either when the stpc consumer is the target of the current pci transaction or when no other de- vice asserts devsel# prior to the subtractive de- code phase of the current pci transaction. par parity signal transactions. this is the parity signal of the pci bus. this signal is used to guar- antee even parity across ad[31:0], cbe#[3:0], and par. this signal is driven by the master dur- ing the address phase and data phase of write transactions. it is driven by the target during data phase of read transactions. (its assertion is identi- cal to that of the ad bus delayed by one pci clock cycle) serr# system error. this is the system error sig- nal of the pci bus. it may, if enabled, be asserted for one pci clock cycle if target aborts a stpc consumer initiated pci transaction. its assertion by either the stpc consumer or by another pci bus agent will trigger the assertion of nmi to the host cpu. this is an open drain output. lock# pci lock. this is the lock signal of the pci bus and is used to implement the exclusive bus operations when acting as a pci target agent. pcireq#[2:0] pci request. this pin are the three external pci master request pins. they indi- cates to the pci arbiter that the external agents desire use of the bus. pcignt#[2:0] pci grant. these pins indicate that the pci bus has been granted to the master re- questing it on its pcireq#. 2.2.6 isa/ide combined address/data la[23]/scs3# unlatched address (isa)/second- ary chip select (ide). this pin has two functions, depending on whether the isa bus is active or the ide bus is active. when the isa bus is active, this pins is isa bus unlatched address bit 23 for 16-bit devices. when isa bus is accessed by any cycle initiated from pci bus, this pin is in output mode. when an isa bus master owns the bus, this pins is in input mode. when the ide bus is active, this signals is used as the active high secondary slave ide chip select signal. this signal is to be externally nanded with the isaoe # signal before driving the ide devices to guarantee it is active only when isa bus is idle. obsolete product(s) - obsolete product(s)
pin description 16/71 issue 2.4 - november 8, 2001 la[22]/scs1# unlatched address (isa)/second- ary chip select (ide) this pin has two functions, depending on whether the isa bus is active or the ide bus is active. when the isa bus is active, this pins is isa bus unlatched address bit 22 for 16-bit devices. when isa bus is accessed by any cycle initiated from pci bus, this pin is in output mode. when an isa bus master owns the bus, this pins is in input mode. when the ide bus is active, this signals is used as the active high secondary slave ide chip select signal. this signal is to be externally anded with the isaoe # signal before driving the ide devices to guarantee it is active only when isa bus is idle. la[21]/pcs3# unlatched address (isa)/primary chip select (ide). this pin has two functions, de- pending on whether the isa bus is active or the ide bus is active. when the isa bus is active, this pins is isa bus unlatched address bit 21 for 16-bit devices. when isa bus is accessed by any cycle initiated from pci bus, this pin is in output mode. when an isa- bus master owns the bus, this pins is in input mode. when the ide bus is active, this signals is used as the active high primary slave ide chip select sig- nal. this signal is to be externally nanded with the isaoe # signal before driving the ide devices to guarantee it is active only when isa bus is idle. la[20]/pcs1# unlatched address (isa)/primary chip select (ide). this pin has two functions, de- pending on whether the isa bus is active or the ide bus is active. when the isa bus is active, this pins is isa bus unlatched address bit 20 for 16-bit devices. when isa bus is accessed by any cycle initiated from pci bus, this pin is in output mode. when an isa bus master owns the bus, this pins is in input mode. when the ide bus is active, this signals is used as the active high primary slave ide chip select sig- nal. this signal is to be externally nanded with the isaoe # signal before driving the ide devices to guarantee it is active only when isa bus is idle. la[19:17]/da[2:0] unlatched address (isa)/ad- dress (ide). these pins are multi-function pins. they are used as the isa bus unlatched address bits [19:17] for isa bus or the three address bits for the ide bus devices. when used by the isa bus, these pins are isa bus unlatched address bits 19-17 on 16-bit devic- es. when isa bus is accessed by any cycle initiat- ed from the pci bus, these pins are in output mode. when an isa bus master owns the bus, these pins are tristated. for ide devices, these signals are used as the da[2:0] and are connected to da[2:0] of ide de- vices directly or through a buffer. if the toggling of signals are to be masked during isa bus cycles, they can be externally ored before being con- nected to the ide devices. sa[19:8]/dd[11:0] unlatched address (isa)/data bus (ide). these are multifunction pins. when the isa bus is active, they are used as the isa bus system address bits 19-8. when the ide bus is ac- tive, they serve as ide signals dd[11:0]. these pins are used as an input when an isa bus master owns the bus and are outputs at all other times. ide devices are connected to sa[19:8] directlyand isa bus is connected to these pins through two ls245 transceivers. the oe of the transceivers are connected to isaoe # and dir is connected to master # . a bus signals of the transceivers are connected to cpc and ide dd bus and b bus sig- nals are connected to isa sa bus. dd[15:12] databus (ide). the high 4 bits of the ide databus are combined with several of the x- bus lines. refer to the following section for x-bus pins for further information. sa[7:0] isa bus address bits [7:0]. these are the 8 low bits of the system address bus of isa on 8- bit slot. these pins are used as an input when an isa bus master owns the bus and are outputs at all other times. sd[15:0] i/o data bus (isa). these pins are the external databus to the isa bus. obsolete product(s) - obsolete product(s)
pin description issue 2.4 - november 8, 2001 17/71 2.2.7 isa/ide combined control iochrdy/diordy channel ready (isa)/busy/ ready (ide). this is a multi-function pin. when the isa bus is active, this pin is iochrdy. when the ide bus is active, this serves as ide signal di- ordy. iochrdy is the io channel ready signal of the isa bus and is driven as an output in response to an isa master cycle targeted to the host bus or an internal register of the stpc consumer. the stpc consumer monitors this signal as an input when performing an isa cycle on behalf of the host cpu, dma master or refresh. isa masters which do not monitor iochrdy are not guaranteed to work with the stpc consumer since the access to the system memory can be considerably delayed due to crt refresh or a write back cycle. 2.2.8 isa control ale address latch enable. this is the address latch enable output of the isa bus and is asserted by the stpc consumer to indicate that la23-17, sa19-0, aen and sbhe# signals are valid. the ale is driven high during refresh, dma master or an isa master cycles by the stpc consumer. ale is driven low after reset. bhe# system bus high enable. this signal, when asserted, indicates that a data byte is being trans- ferred on sd15-8 lines. it is used as an input when an isa master owns the bus and is an output at all other times. memr# memory read. this is the memory read command signal of the isa bus. it is used as an in- put when an isa master owns the bus and is an output at all other times. the memr# signal is active during refresh. memw# memory write. this is the memory write command signal of the isa bus. it is used as an in- put when an isa master owns the bus and is an output at all other times. smemr# system memory read. the stpc con- sumer generates smemr# signal of the isa bus only when the address is below one megabyte or the cycle is a refresh cycle. smemw# system memory write. the stpc con- sumer generates smemw# signal of the isa bus only when the address is below one megabyte. ior# i/o read. this is the io read command sig- nal of the isa bus. it is an input when an isa mas- ter owns the bus and is an output at all other times. iow# i/o write. this is the io write command sig- nal of the isa bus. it is an input when an isa mas- ter owns the bus and is an output at all other times. master# add on card owns bus. this signal is active when an isa device has been granted bus ownership. mcs16# memory chip select16. this is the de- code of la23-17 address pins of the isa address bus without any qualification of the command sig- nal lines. mcs16# is always an input. the stpc consumer ignores this signal during io and re- fresh cycles. iocs16# io chip select16. this signal is the de- code of sa15-0 address pins of the isa address bus without any qualification of the command sig- nals. the stpc consumer does not drive iocs16# (similar to pc-at design). an isa mas- ter access to an internal register of the stpc con- sumer is executed as an extended 8-bit io cycle. ref# refresh cycle. this is the refresh command signal of the isa bus. it is driven as an output when the stpc consumer performs a refresh cy- cle on the isa bus. it is used as an input when an isa master owns the bus and is used to trigger a refresh cycle. the stpc consumer performs a pseudo hidden refresh. it requests the host bus for two host clocks to drive the refresh address and capture it in external buffers. the host bus is then relin- quished while the refresh cycle continues on the isa bus. aen address enable. address enable is enabled when the dma controller is the bus owner to indi- cate that a dma transfer will occur. the enabling of the signal indicates to io devices to ignore the ior#/iow# signal during dma transfers. obsolete product(s) - obsolete product(s)
pin description 18/71 issue 2.4 - november 8, 2001 zws# zero wait state. this signal, when assert- ed by addressed device, indicates that current cy- cle can be shortened. iochck# io channel check. io channel check is enabled by any isa device to signal an error condition that can not be corrected. nmi signal be- comes active upon seeing iochck# active if the corresponding bit in port b is enabled. isaoe# bidirectional oe control. this signal con- trols the oe signal of the external transceiver that connects the ide dd bus and isa sa bus. gpiocs# i/o general purpose chip select 1. this output signal is used by the external latch on isa bus to latch the data on the sd[7:0] bus. the latch can be use by pmu unit to control the exter- nal peripheral devices to power down or any other desired function. 2.2.9 ide control pirq primary interrupt request. interrupt request from primary ide channel. sirq secondary interrupt request. interrupt re- quest from secondary ide channel. pdrq primary dma request. dma request from primary ide channel. sdrq secondary dma request. dma request from secondary ide channel. pdack# primary dma acknowledge. dma ack- noledge to primary ide channel. sdack# secondary dma acknowledge. dma acknoledge to secondary ide channel. pior# primary i/o read. primary channel read. active low output. piow# primary i/o write . primary channel write. active low output. sior# secondary i/o read secondary channel read. active low output. siow# secondary i/o write secondary channel write. active low output. 2.2.10 ipc irq_mux[3:0] multiplexed interrupt request. these are the isa bus interrupt signals. they are to be encoded before connection to the stpc consumer using isaclk and isaclkx2 as the input selection strobes. note that irq8b, which by convention is connect- ed to the rtc, is inverted before being sent to the interrupt controller, so that it may be connected di- rectly to the irq pin of the rtc. pci_int[3:0] pci interrupt request. these are the pci bus interrupt signals. they are to be en- coded before connection to the stpc consumer using isaclk and isaclkx2 as the input selec- tion strobes. dreq_mux[1:0] isa bus multiplexed dma re- quest. these are the isa bus dma request sig- nals. they are to be encoded before connection to the stpc consumer using isaclk and isaclkx2 as the input selection strobes. dack_enc[2:0] dma acknowledge. these are the isa bus dma acknowledge signals. they are encoded by the stpc consumer before output and should be decoded externally using isaclk and isaclkx2 as the control strobes. tc isa terminal count. this is the terminal count output of the dma controller and is connected to the tc line of the isa bus. it is asserted during the last dma transfer, when the byte count expires. spkrd speaker drive. this the output to the speaker and is and of the counter 2 output with bit 1 of port 61, and drives an external speaker driver. this output should be connected to 7407 type high voltage driver. obsolete product(s) - obsolete product(s)
pin description issue 2.4 - november 8, 2001 19/71 2.2.11 x-bus interface pins / ide data rmrtccs# / dd[15] rom/real time clock chip select. this pin is a multi-function pin. when isaoe# is active, this signal is used as rm- rtccs#. this signal is asserted if a rom access is decoded during a memory cycle. it should be combined with memr# or memw# signals to properly access the rom. during a io cycle, this signal is asserted if access to the real time clock (rtc) is decoded. it should be combined with ior or iow# signals to properly access the real time clock. when isaoe# is inactive, this signal is used as ide dd[15] signal. this signal must be ored externally with isaoe# and is then connected to rom and rtc. an ls244 or equivalent function can be used if oe# is connected to isaoe# and the output is provided with a weak pull-up resistor. kbcs# / dd[14] keyboard chip select. this pin is a multi-function pin. when isaoe# is active, this signal is used as kbcs#. this signal is assert- ed if a keyboard access is decoded during a i/o cycle. when isaoe# is inactive, this signal is used as ide dd[14] signal. this signal must be ored externally with isaoe# and is then connected to keyboard. an ls244 or equivalent function can be used if oe# is connect- ed to isaoe# and the output is provided with a weak pull-up resistor. rtcrw# / dd[13] real time clock rw . this pin is a multi-function pin. when isaoe# is active, this signal is used as rtcrw#. this signal is as- serted for any i/o write to port 71h. when isaoe# is inactive, this signal is used as ide dd[13] signal. this signal must be ored ex- ternally with isaoe# and then connected to the rtc. an ls244 or equivalent function can be used if oe is connected to isaoe# and the output is provided with a weak pull-up resistor. rtcds# / dd[12] real time clock ds . this pin is a multi-function pin. when isaoe# is active, this signal is used as rtcds#. this signal is asserted for any i/o read to port 71h. its polarity complies with the ds pin of the mt48t86 rtc device when configured with intel timings. when isaoe# is inactive, this signal is used as ide dd[12] signal. this signal must be ored ex- ternally with isaoe# and is then connected to rtc. an ls244 or equivalent function can be used if oe# is connected to isaoe# and the out- put is provided with a weak pull-up resistor. rtcas real time clock address strobe. this sig- nal is asserted for any i/o write to port 70h. 2.2.12 monitor interface red, green, blue rgb video outputs. these are the 3 analog color outputs from the ram- dacs. these signals are sensitive to interference, therefore they need to be properly shielded. vsync vertical synchronisation pulse. this is the vertical synchronization signal from the vga controller. hsync horizontal synchronisation pulse. this is the horizontal synchronization signal from the vga controller. vref_dac dac voltage reference. an external voltage reference is connected to this pin to bias the dac. rset resistor current set. this is reference cur- rent input to the ramdac is used to set the full- scale output of the ramdac. comp compensation. this is the ramdac com- pensation pin. normally, an external capacitor (typically 10nf) is connected between this pin and v dd to damp oscillations. ddc[1:0] direct data channel serial link. these bidirectional pins are connected to crtc register 3fh to implement ddc capabilities. they conform to i 2 c electrical specifications, they have open- collector output drivers which are internally con- nected to v dd through pull-up resistors. they can instead be used for accessing i2c devic- es on board. ddc1 and ddc0 correspond to scl and sda respectively. 2.2.13 miscellaneous scan_enable reserved . the pins are re- served for test and miscellaneous functions) obsolete product(s) - obsolete product(s)
pin description 20/71 issue 2.4 - november 8, 2001 table 2-3. pinout. pin # pin name af3 sysrsti a3 xtali c4 xtalo g23 hclk f25 dev_clk af15 gclk2x af9 dclk ad15 ma[0] af16 ma[1] ac15 ma[2] ae17 ma[3] ad16 ma[4] af17 ma[5] ac17 ma[6] ae18 ma[7] ad17 ma[8] af18 ma[9] ae19 ma[10] af19 ma[11] ad18 ras#[0] ae20 ras#[1] ac19 ras#[2] af20 ras#[3] ae21 cas#[0] ac20 cas#[1] af21 cas#[2] ad20 cas#[3] ae22 cas#[4] af22 cas#[5] ad21 cas#[6] ae23 cas#[7] ac22 mwe# af23 md[0] ae24 md[1] af24 md[2] ad25 md[3] ac25 md[4] ac26 md[5] ab24 md[6] aa25 md[7] aa24 md[8] y25 md[9] y24 md[10] v23 md[11] w24 md[12] v26 md[13] v24 md[14] u23 md[15] u24 md[16] r26 md[17] p25 md[18] p26 md[19] n25 md[20] n26 md[21] m25 md[22] m26 md[23] m24 md[24] m23 md[25] l24 md[26] j25 md[27] j26 md[28] h26 md[29] g25 md[30] g26 md[31] ad22 md[32] ad23 md[33] ae26 md[34] ad26 md[35] ac24 md[36] ab25 md[37] ab26 md[38] y23 md[39] aa26 md[40] y26 md[41] w25 md[42] w26 md[43] v25 md[44] u25 md[45] u26 md[46] t25 md[47] r25 md[48] t24 md[49] r23 md[50] r24 md[51] n23 md[52] p24 md[53] n24 md[54] l25 md[55] l26 md[56] k25 md[57] k26 md[58] k24 md[59] h25 md[60] j24 md[61] h23 md[62] h24 md[63] f24 pci_clki pin # pin name d25 pci_clko a20 ad[0] c20 ad[1] b19 ad[2] a19 ad[3] c19 ad[4] b18 ad[5] a18 ad[6] b17 ad[7] c18 ad[8] a17 ad[9] d17 ad[10] b16 ad[11] c17 ad[12] b15 ad[13] a15 ad[14] c16 ad[15] d15 ad[16] a14 ad[17] c15 ad[18] b13 ad[19] d13 ad[20] a13 ad[21] c14 ad[22] c13 ad[23] a12 ad[24] b11 ad[25] c12 ad[26] a11 ad[27] d12 ad[28] b10 ad[29] c11 ad[30] a10 ad[31] d10 cbe[0] c10 cbe[1] a9 cbe[2] b8 cbe[3] a8 frame# b7 trdy# d8 irdy# a7 stop# c8 devsel# b6 par d7 serr# a6 lock# c21 pci_req#[0] a21 pci_req#[1] b20 pci_req#[2] c22 pci_gnt#[0] pin # pin name obsolete product(s) - obsolete product(s)
pin description issue 2.4 - november 8, 2001 21/71 b21 pci_gnt#[1] d20 pci_gnt#[2] a5 pci_int[0] c6 pci_int[1] b4 pci_int[2] d5 pci_int[3] f2 la[17]/da[0] g4 la[18]/da[1] f3 la[19]/da[2] f1 la[20]/pcs1# g2 la[21]/pcs3# g3 la[22]/scs1# h2 la[23]/scs3# j4 sa[0] h1 sa[1] h3 sa[2] j2 sa[3] j1 sa[4] k2 sa[5] j3 sa[6] k1 sa[7] k4 sa[8]/dd[0] l2 sa[9]/dd[1] k3 sa[10]/dd[2] l1 sa[11]/dd[3] m2 sa[12] / dd[4] m1 sa[13] / dd[5] l3 sa[14] / dd[6] n2 sa[15] / dd[7] m4 sa[16] / dd[8] n1 sa[17] / dd[9] m3 sa[18] / dd[10] p4 sa[19] / dd[11] p3 rtcds# / dd[12] r2 rtcrw# / dd[13] n3 kbcs# / dd[14] p1 rmrtccs# / dd[15] r1 sd[0] t2 sd[1] r3 sd[2] t1 sd[3] r4 sd[4] u2 sd[5] t3 sd[6] u1 sd[7] u4 sd[8] v2 sd[9] u3 sd[10] pin # pin name v1 sd[11] w2 sd[12] w1 sd[13] v3 sd[14] y2 sd[15] y1 iochrdy ae4 sysrsto# ad4 isa_clk ae5 isa_clk2x af8 osc14m w3 ale ac9 zws# aa2 bhe# y4 memr# aa1 memw# y3 smemr# ab2 smemw# aa3 ior# ac2 iow# ab4 master# ac1 mcs16# ab3 iocs16# ad2 ref# ac3 aen ad1 iochck# af2 isaoe# a4 rtcas ae3 gpiocs# b1 pirq c2 sirq c1 pdrq d2 sdrq d3 pdack# d1 sdack# e2 pior# e4 piow# e3 sior# e1 siow# e23 irq_mux[0] d26 irq_mux[1] e24 irq_mux[2] c25 irq_mux[3] a24 dreq_mux[0] b23 dreq_mux[1] c23 dack_enc[0] pin # pin name a23 dack_enc[1] b22 dack_enc[2] d22 tc c5 spkrd ae6 red ad6 green af6 blue ad5 vsync ac5 hsync ad7 vref_dac ae8 rset af5 comp c7 sda / ddc[0] b5 scl / ddc[1] ac12 vclk ae13 vin[0] ad14 vin[1] ad12 vin[2] ae14 vin[3] ac14 vin[4] af14 vin[5] ad13 vin[6] ae15 vin[7] af10 red_tv ac10 green_tv af11 blue_tv ae10 vcs ad9 odd_even ad11 cvbs ad8 iref1_tv ae9 vref1_tv ae11 iref2_tv ad10 vref2_tv b3 scan_enable af12 vdda_tv ac7 vdd_dac1 af4 vdd_dac2 ad19 vdd_gclk_pll af13 vdd_dclk_pll f26 vdd_hclk_pll g24 vdd_devclk_pll a16 vdd5 b12 vdd5 b9 vdd5 pin # pin name obsolete product(s) - obsolete product(s)
pin description 22/71 issue 2.4 - november 8, 2001 d18 vdd5 a22 vdd b14 vdd c9 vdd d6 vdd d11 vdd d16 vdd d21 vdd f4 vdd f23 vdd g1 vdd k23 vdd l4 vdd l23 vdd p2 vdd t4 vdd t23 vdd t26 vdd w4 vdd aa4 vdd aa23 vdd ab1 vdd ab23 vdd ac6 vdd ac11 vdd ac16 vdd ac21 vdd ae12 vssa_tv ae7 vss_dac1 af7 vss_dac2 e25 vss_dll e26 vss_dll a1:2 vss a26 vss b2 vss b25:26 vss c3 vss c24 vss d4 vss d9 vss d14 vss d19 vss d23 vss h4 vss j23 vss l11:16 vss m11:16 vss n4 vss pin # pin name n11:16 vss p11:16 vss p23 vss r11:16 vss t11:16 vss v4 vss w23 vss ac4 vss ac8 vss ac13 vss ac18 vss ac23 vss ad3 vss ad24 vss ae1:2 vss ae16 vss ae25 vss af1 vss af25 vss af26 vss c26 reserved d24 reserved b24 reserved a25 reserved pin # pin name obsolete product(s) - obsolete product(s)
strap option issue 2.4 - november 8, 2001 23/71 3. strap option this chapter defines the stpc consumer strap options and their location. memory data lines note designation location actual settings set to 0 set to 1 md0 1 index 4a, bit 0 user defined color_sel smemw# md16 reserved index 4c,bit 0 pull up - - md17 pci_clko divisor index 4c,bit 1 user defined hclk / 2 hclk / 3 md18 reserved index 4c,bit 2 pull up - - md19 reserved index 4c,bit 3 pull up - - md20 reserved index 4c, bit4 pull up - - md21 reserved index 5f, bit 0 pull up - - md22 reserved index 5f, bit 1 pull up - - md23 reserved index 5f,bit 2 pull up - - md24 hclk pll speed index 5f,bit 3 user defined see 3.1.4 md25 [26:24] index 5f,bit 4 md26 index 5f,bit 5 md27 reserved - pull down - - md28 reserved - pull down - - md29 reserved - pull down - - md30 reserved - pull down - - md31 reserved - pull down - - md32 reserved - pull down - - md33 reserved - pull up - - md34 reserved - pull down - - md35 reserved - pull down - - md36 reserved - pull up - - md37 reserved - pull up - - md38 reserved - pull up - - md39 reserved - pull up - - md40 cpu mode user defined dx1 dx2 md41 reserved - pull down - - md42 reserved - pull up - - md43 reserved - pull down - - note 1: this strap option selects between two different functional blocks, the first is the isa (smemw#) and the other is the vga block (color_key). obsolete product(s) - obsolete product(s)
strap option 24/71 issue 2.4 - november 8, 2001 3.1. strap register description 3.1.1. strap register 0 this register reflect the status of pins md[7:0] respectively. they are expected to be connected on the system board to the simm configuration pins as follows: note that the simm speed and type information read here is meant only for the software and is not used by the hardware. the software must program the host and graphics dram controller configuration regis- ters appropriately based on these bits. strap0 access = 0022h/0023h regoffset = 04ah 76543210 md[7] md[6] md[5] md[4] md[3] md[2] rsv this register defaults to the values sampled on md[7:0] pins after reset bit number sampled mnemonic description bits 7-2 md[7:2] available for user bits 1-0 rsv reserved. obsolete product(s) - obsolete product(s)
strap option issue 2.4 - november 8, 2001 25/71 3.1.2. strap register 1 this register reflect the status of pins md[15:8] respectively. they are expected to be connected on the system board to the simm configuration pins as follows: note that the simm speed and type information read here is meant only for the software and is not used by the hardware. the software must program the host and graphics dram controller configuration regis- ters appropriately based on these bits. strap1 access = 0022h/0023h regoffset = 04bh 76543210 md[15] md[14] md[13] md[12] md[11] md[10] md[9] md[8] this register defaults to the values sampled on md[15:8] pins after reset bit number sampled mnemonic description bits 7-0 md[15:8] available for user obsolete product(s) - obsolete product(s)
strap option 26/71 issue 2.4 - november 8, 2001 3.1.3. strap register 2 bits 4-0 of this register reflect the status of pins md[20:16] respectively. bit 5 of this register reflect the sta- tus of pin md[23]. bit 4 is writeable, writes to other bits in this register have no effect. strap2 access = 0022h/0023h regoffset = 04ch 76543210 rsv md[17] rsv this register defaults to the values sampled on md[23] and md[20:16] pins after reset bit number sampled mnemonic description bits 7-2 rsv reserved bit 1 this bit reflects the value sampled on md[17] pin and controls the pci clock output as follows: setting to 0, the pci clock output = hclk / 2, setting to 1, the pci clock output = hclk / 3. bit 0 rsv reserved. obsolete product(s) - obsolete product(s)
strap option issue 2.4 - november 8, 2001 27/71 3.1.4. hclk pll strap register 0 bits 5-0 of this register reflect the status of pins md[26:21] respectively. they are use by the chip as fol- lows: programming notes: strap options [39:27] are reserved. hclk_strap0 access = 0022h/0023h regoffset = 05fh 76543210 rsv md[26] md[25] md[24] rsv this register defaults to the values sampled on pins described below after reset bit number sampled mnemonic description bits 7-6 rsv reserved bits 5-3 md[26:24] these pins reflect the value sampled on md[26:24] pins respectively and control the host clock frequency synthesizer. 000: 25 mhz 001: 33 mhz 010: 40 mhz 011: 50 mhz 100: 60 mhz 101: 66 mhz 110: 75 mhz 111: 80 mhz bits 2-0 rsv reserved. obsolete product(s) - obsolete product(s)
strap option 28/71 issue 2.4 - november 8, 2001 3.1.5. 486 clock programming (486_clk) the bit md[40] is used to set the clock multiplication factor of the 486 core. with the md[40] pin pulled low the 486 will run in dx (x1) mode, while with the md[40] pin pulled high the 486 will run in dx2 (x2) mode. the default value of the resistor on this strap input should be a resister to ground (dx mode). strap options md[43:41] are reserved. obsolete product(s) - obsolete product(s)
electrical specifications issue 2.4 - november 8, 2001 29/71 4. electrical specifications 4.1 introduction the electrical specifications in this chapter are val- id for the stpc consumer. 4.2 electrical connections 4.2.1 power/ground connections/decoupling due to the high frequency of operation of the stpc consumer, it is necessary to install and test this device using standard high frequency tech- niques. the high clock frequencies used in the stpc consumer and its output buffer circuits can cause transient power surges when several output buffers switch output levels simultaneously. these effects can be minimized by filtering the dc power leads with low-inductance decoupling capacitors, using low impedance wiring, and by utilizing all of the vss and vdd pins. 4.2.2 unused input pins all inputs not used by the designer and not listed in the table of pin connections in chapter 3 should be connected either to vdd or to vss. connect active-high inputs to vdd through a 20 k w (10%) pull-down resistor and active-low inputs to vss and connect active-low inputs to vcc through a 20 k w (10%) pull-up resistor to prevent spurious operation. 4.2.3 reserved designated pins pins designated reserved should be left discon- nected. connecting a reserved pin to a pull-up re- sistor, pull-down resistor, or an active signal could cause unexpected results and possible circuit malfunctions. 4.3 absolute maximum ratings the following table lists the absolute maximum ratings for the stpc consumer device. stresses beyond those listed under table 4-1 limits may cause permanent damage to the device. these are stress ratings only and do not imply that oper- ation under any conditions other than those spec- ified in section "operating conditions". exposure to conditions beyond table 4-1 may (1) reduce device reliability and (2) result in prema- ture failure even when there is no immediately ap- parent sign of failure. prolonged exposure to con- ditions at or near the absolute maximum ratings ( table 4-1 ) may also result in reduced useful life and reliability. table 4-1. absolute maximum ratings symbol parameter value units v ddx dc supply voltage -0.3, 4.0 v v i , v o digital input and output voltage -0.3, vdd + 0.3 v t stg storage temperature -40, +150 c t oper operating temperature 0, +70 c p tot total power dissipation of the package 4.8 w obsolete product(s) - obsolete product(s)
electrical specifications 30/71 issue 2.4 - november 8, 2001 4.4 dc characteristics table 4-2. dc characteristics recommended operating conditions : vdd = 3.3v 0.3v, tcase = 0 to 100 c unless otherwise specified symbol parameter test conditions min typ max unit v dd operating voltage 3.0 3.3 3.6 v p dd supply power v dd = 3.3v, h clk = 66mhz 3.2 3.9 w v ref_dac dac voltage reference 1.215 1.235 1.255 v v ol output low voltage i load =1.5 to 8ma depending of the pin 0.5 v v oh output high voltage i load =-0.5 to -8ma depending of the pin 2.4 v v il input low voltage except xtali -0.3 0.8 v xtali -0.3 0.9 v v ih input high voltage except xtali 2.1 v dd +0.3 v xtali 2.35 v dd +0.3 v i lk input leakage current input, i/o -5 5 m a obsolete product(s) - obsolete product(s)
electrical specifications issue 2.4 - november 8, 2001 31/71 4.5 ac characteristics table 4-4 through table 4-9 list the ac character- istics including output delays, input setup require- ments, input hold requirements and output float delays. these measurements are based on the measurement points identified in figure 4-1 . the rising clock edge reference level vref , and other reference levels are shown in table 4-3 below for the stpc consumer. input or output signals must cross these levels during testing. figure 4-1 shows output delay (a and b) and input setup and hold times (c and d). input setup and hold times (c and d) are specified minimums, de- fining the smallest acceptable sampling window a synchronous input signal must be stable for cor- rect operation. note: refer to figure 4-1 . table 4-3. drive level and measurement points for switching characteristics symbol value units v ref 1.5 v v ihd 3.0 v v ild 0.0 v figure 4-1 drive level and measurement points for switching characteristics clk: v ref v ild v ihd tx legend: a - maximum output delay specification b - minimum output delay specification c - minimum input setup specification d - minimum input hold specification v ref valid valid valid outputs: inputs: output n output n+1 input max min a b cd v ref v ild v ihd obsolete product(s) - obsolete product(s)
electrical specifications 32/71 issue 2.4 - november 8, 2001 figure 4-2 clk timing measurement points note; the above timin g s are g eneric timin g s and are not specific to the interfaces defined below clk t5 t4 t3 v ref v il (max) v ih (min) t2 t1 legend: t1 - one clock cycle t2 - minimum time at v ih t3 - minimum time at v il t4 - clock fall time t5 - clock rise time note; all signals are sampled on the rising edge of the clk. obsolete product(s) - obsolete product(s)
electrical specifications issue 2.4 - november 8, 2001 33/71 4.5.1 power on sequence figure 4-3 describes the power-on sequence of the stpc, also called cold reset. there is no constraint on the rising edge of sysrsti#. it just needs to stay low at least 10 m s after power supply is stable to let the stpc plls stabilize. strap options are continuously sampled during sysrsti# low and must remain stable. once sysrsti# is high, they must not change until sysrsto# goes high. bus activity starts only few clock cycles after the release of sysrsto#. the t oggling signals de- pend on the stpc configuration. in isa mode, activity is visible on pci prior to the isa bus as the controller is part of the south bridge (cpc). in local bus mode, the pci bus is not accessed and the flash chip select is the control signal to monitor. obsolete product(s) - obsolete product(s)
electrical specifications 34/71 issue 2.4 - november 8, 2001 figure 4-3. power-on timing diagram strap options power supplies sysrsti# sysrsto# 14 mhz 1.6 v valid configuration > 10 us hclk pci_clk 2.3 ms isaclk obsolete product(s) - obsolete product(s)
electrical specifications issue 2.4 - november 8, 2001 35/71 4.5.2 reset sequence figure 4-4 describes the reset sequence of the stpc, also called warm reset. the constraints on the strap options and the bus activities are the same as for the cold reset. it is mandatory to have a clean reset pulse without glitches as the stpc could then sample invalid strap option setting and enter into an umpredicta- ble mode. while sysrsti# is active, the pci clock pll runs in open loop mode at a speed of few 100s khz. fi g ure 4-4. reset timin g dia g ram strap options sysrsti# sysrsto# 14 mhz valid configuration hclk pci_clk 2.3 ms isaclk 1.6 v md[63:0] obsolete product(s) - obsolete product(s)
electrical specifications 36/71 issue 2.4 - november 8, 2001 4.5.3 dram controller ac timing charcteristics figure 4-5 read mode (ref table table 4-4 ) row column trch tcpn trcs tcah tcoh tcpn tcrp trp trc tras tral trp tras trah trad tchr trcd trc tcrd tccas tcras tcma clk ras# cas# ma mwe# md figure 4-6 memory early write mode (ref table table 4-4 ) row column data valid tcpn tcpn tcwl trch tchr twrh tcpn tds twch twcs trcs tcah tcpn trp trc tcrw trwl tras tral trp tdhr twcr trad tras trah tchr trcd trc tcrp tccas tcras tcma clk ras# cas# ma mwe# md obsolete product(s) - obsolete product(s)
electrical specifications issue 2.4 - november 8, 2001 37/71 figure 4-7 edo read mode (ref table table 4-4 ) figure 4-8 edo write mode (ref table table 4-4 ) row column row open valid data open tcpn tcpn tcpn tcoh trcs tcah tcpn trch tral tras trc trah trad tar trcd tcrp tcsr tchr tras trp trp trc tcmd tcmwe tccas tcras tcma clk ras# cas# ma mwe# md row column row open valid data open tcpn tcpn tcpn tcoh trcs tcah tcpn trch tral tras trc trah trad tar trcd tcrp tcsr tchr tras trp trp trc tcmd tcmwe tccas tcras tcma clk ras# cas# ma mwe# md obsolete product(s) - obsolete product(s)
electrical specifications 38/71 issue 2.4 - november 8, 2001 figure 4-9 fast page mode read (ref table table 4-4 ) figure 4-10 fast page mode write (ref table table 4-4 ) ro w column 1 column 2 column n dout 1 dout 2 dout n tcpn tcoh tcah tcpn tcpn tcoh tcah tcpn tcpn tcoh tcah tcpn tcrp trp tral trp tar trah tcsh trad trcd tcrp tcmd tcras tcmd tcma tccas tcmd tcma tccas tcma tccas tcras clk ras# cas# ma mwe# md row column 1 column 2 column n dout 1 dout 2 dout n tral trch tcpn tds tcah tcpn tcpn tds trc tcah tcpn tcwl tcpn tds twcs trc tcah tcpn tcrp trp tcrw trwl tras tral trp tdhr twcr tar tras trah tcsh trad trcd tcrp tcmd tccas tcma tcras clk ras# cas# ma mwe# oe md obsolete product(s) - obsolete product(s)
electrical specifications issue 2.4 - november 8, 2001 39/71 figure 4-11 refresh cycle (ref table table 4-4 ) tcpn tcpn tcpn tcpn tcsr trp trpc tras trp tchr tcrs tcsr tras trp trpc trp tcras tccas clk ma[11:0] ras#[3:0] cas#[7:0] obsolete product(s) - obsolete product(s)
electrical specifications 40/71 issue 2.4 - november 8, 2001 table 4-4. ac memory timing characteristics parameter min max units tcras hclk (or gclk2x) to ras#[3:0] valid (see note 3) 17 ns tccas hclk (or gclk2x) to cas#[7:0] bus valid (see note 3) 17 ns tcma hclk (or gclk2x) to ma[11:0] bus valid (see note 3) 17 ns tcmwe hclk (or gclk2x) to mwe# valid (see note 3) 17 ns tcmd hclk to md[63:0] bus valid (see note 3) 25 ns tgcmd gclk2x to md[63:0] bus valid (see note 3) 23 ns tmdg md[63:0] generic hold 0 ns tcah column address hold time 3 1t cycles ns tchr cas hold time 3 1t cycles ns tcoh data hold time from cas low note 1 ns tcpn cas precharge time 1t cycles ns tcrp cas to ras precharge time 1t cycles tcrw cas low to ras high (write only) 3 1t cycles ns tcsr cas setup time 3 1t cycles ns tds data in setup time 3 1t cycles ns trah row address hold time 3 1t cycles ns tras ras pulse width 3 3t cycles ns trc random read or write time cycle 3 6t cycles ns trcd ras to cas delay time 3 1t cycles ns trch read command hold time 3 1t cycles ns trcs read command setup time 3 1t cycles ns trp ras precharge time 3 2t cycles ns twch write command hold time 3 1t cycles ns twcs we command setup time 3 1t cycles ns twrh we hold time note 2 ns twrp we setup time 3 1t cycles ns tar column address hold time from ras 3 1t cycles ns trad ras to valid column address delay 3 1t cycles ns tral column address to ras setup time 3 2t cycles ns twcr write command hold reference to ras 3 1t cycles ns trwl write command to ras setup time (note 2) 3 1t cycles ns tcwl write command to cas setup time (note 2) 3 1t cycles ns tdhr data hold reference to ras 3 3t cycles ns trpc ras high to cas low precharge 3 1t cycles ns tcrs cas before ras setup time 3 1t cycles ns tchr cas before ras hold time 3 1t cycles ns tcsh cas hold time after ras 3 1t cycles ns note 1; t cycle x n cas + (t data off - t cas out ) where t cycle is the the number of clock cycles. n cas is the number of cas cycles (see section 6.7. ) t dataoff is the generic datahold t cas out the clk (either hclk or gclk2x) to cas low. t dataoff and t cas out are used to refine the timing programming. note 2; value to be derived from cas pulse width which is programmable (see section 6.7. ). note 3; for all chronograms, clk refers to the clock signal that the program is using. it can be either hclk or gclk2x obsolete product(s) - obsolete product(s)
electrical specifications issue 2.4 - november 8, 2001 41/71 4.5.4 pci interface table 4-5 lists the ac characteristics of the pci in- terface. table 4-5. pci bus ac timing name parameter min max unit t1 pci_clki to ad[31:0] valid 2 11 ns t2 pci_clki to frame# valid 2 11 ns t3 pci_clki to cbe#[3:0] valid 2 11 ns t4 pci_clki to par valid 2 11 ns t5 pci_clki to trdy# valid 2 11 ns t6 pci_clki to irdy# valid 2 11 ns t7 pci_clki to stop# valid 2 11 ns t8 pci_clki to devsel# valid 2 11 ns t9 pci_clki to pci_gnt# valid 2 12 ns t10 ad[31:0] bus setup to pci_clki 5 ns t11 ad[31:0] bus hold from pci_clki 0 ns t12 pci_req#[2:0] setup to pci_clki 4 ns t13 pci_req#[2:0] hold from pci_clki 4 ns t14 cbe#[3:0] setup to pci_clki 5 ns t15 cbe#[3:0] hold to pci_clki 0 ns t16 irdy# setup to pci_clki 5 ns t17 irdy# hold to pci_clki 0 ns t18 frame# setup to pci_clki 5 ns t19 frame# hold from pci_clki 0 ns obsolete product(s) - obsolete product(s)
electrical specifications 42/71 issue 2.4 - november 8, 2001 4.5.5 isa interface ac timing characteristics table 4-12 and table 4-6 list the ac characteris- tics of the isa interface. figure 4-12 isa cycle (ref table 4-6 ) note 1: stands for smemr#, smemw#, memr#, memw#, ior# & iow#. the clock has not been represented as it is dependent on the isa slave mode. valid aenx valid address valid address, sbhe* v.dat a valid data 54 28 26 64 59 58 55 28 23 61 48 47 26 23 57 27 24 42 41 10 11 34 33 3 22 56 29 25 9 18 2 12 38 37 15 14 13 12 ale aen la [23:17] sa [19:0] control (note 1) iocs16# mcs16# iochrdy read data write data table 4-6. isa bus ac timing name parameter min max units 2 la[23:17] valid before ale# negated 5t cycles 3 la[23:17] valid before memr#, memw# asserted 3a memory access to 16-bit isa slave 5t cycles 3b memory access to 8-bit isa slave 5t cycles 9 sa[19:0] & sbhe valid before ale# negated 1t cycles 10 sa[19:0] & sbhe valid before memr#, memw# asserted 10a memory access to 16-bit isa slave 2t cycles 10b memory access to 8-bit isa slave 2t cycles 10 sa[19:0] & shbe valid before smemr#, smemw# asserted note: the si g nal numberin g refers to table 4-12 obsolete product(s) - obsolete product(s)
electrical specifications issue 2.4 - november 8, 2001 43/71 10c memory access to 16-bit isa slave 2t cycle 10d memory access to 8-bit isa slave 2t cycle 10e sa[19:0] & sbhe valid before ior#, iow# asserted 2t cycles 11 isaclk2x to iow# valid 11a memory access to 16-bit isa slave - 2bclk 2t cycles 11b memory access to 16-bit isa slave - standard 3bclk 2t cycles 11c memory access to 16-bit isa slave - 4bclk 2t cycles 11d memory access to 8-bit isa slave - 2bclk 2t cycles 11e memory access to 8-bit isa slave - standard 3bclk 2t cycles 12 ale# asserted before ale# negated 1t cycles 13 ale# asserted before memr#, memw# asserted 13a memory access to 16-bit isa slave 2t cycles 13b memory access to 8-bit isa slave 2t cycles 13 ale# asserted before smemr#, smemw# asserted 13c memory access to 16-bit isa slave 2t cycles 13d memory access to 8-bit isa slave 2t cycles 13e ale# asserted before ior#, iow# asserted 2t cycles 14 ale# asserted before al[23:17] 14a non compressed 15t cycles 14b compressed 15t cycles 15 ale# asserted before memr#, memw#, smemr#, smemw# negated 15a memory access to 16-bit isa slave- 4 bclk 11t cycles 15e memory access to 8-bit isa slave- standard cycle 11t cycles 18a ale# negated before la[23:17] invalid (non compressed) 14t cycles 18a ale# negated before la[23:17] invalid (compressed) 14t cycles 22 memr#, memw# asserted before la[23:17] 22a memory access to 16-bit isa slave. 13t cycles 22b memory access to 8-bit isa slave. 13t cycles 23 memr#, memw# asserted before memr#, memw# negated 23b memory access to 16-bit isa slave standard cycle 9t cycles 23e memory access to 8-bit isa slave standard cycle 9t cycles 23 smemr#, smemw# asserted before smemr#, smemw# negated 23h memory access to 16-bit isa slave standard cycle 9t cycles 23l memory access to 16-bit isa slave standard cycle 9t cycles 23 ior#, iow# asserted before ior#, iow# negated 23o memory access to 16-bit isa slave standard cycle 9t cycles 23r memory access to 8-bit isa slave standard cycle 9t cycles 24 memr#, memw# asserted before sa[19:0] 24b memory access to 16-bit isa slave standard cycle 10t cycles 24d memory access to 8-bit isa slave - 3blck 10t cycles 24e memory access to 8-bit isa slave standard cycle 10t cycles 24f memory access to 8-bit isa slave - 7bclk 10t cycles 24 smemr#, smemw# asserted before sa[19:0] 24h memory access to 16-bit isa slave standard cycle 10t cycles 24i memory access to 16-bit isa slave - 4bclk 10t cycles 24k memory access to 8-bit isa slave - 3bclk 10t cycles table 4-6. isa bus ac timing name parameter min max units note: the si g nal numberin g refers to table 4-12 obsolete product(s) - obsolete product(s)
electrical specifications 44/71 issue 2.4 - november 8, 2001 24l memory access to 8-bit isa slave standard cycle 10t cycles 24 ior#, iow# asserted before sa[19:0] 24o i/o access to 16-bit isa slave standard cycle 19t cycles 24r i/o access to 16-bit isa slave standard cycle 19t cycles 25 memr#, memw# asserted before next ale# asserted 25b memory access to 16-bit isa slave standard cycle 10t cycles 25d memory access to 8-bit isa slave standard cycle 10t cycles 25 smemr#, smemw# asserted before next ale# asserted 25e memory access to 16-bit isa slave - 2bclk 10t cycles 25f memory access to 16-bit isa slave standard cycle 10t cycles 25h memory access to 8-bit isa slave standard cycle 10t cycles 25 ior#, iow# asserted before next ale# asserted 25i i/o access to 16-bit isa slave standard cycle 10t cycles 25k i/o access to 16-bit isa slave standard cycle 10t cycles 26 memr#, memw# asserted before next memr#, memw# asserted 26b memory access to 16-bit isa slave standard cycle 12t cycles 26d memory access to 8-bit isa slave standard cycle 12t cycles 26 smemr#, smemw# asserted before next smemr#, smemw# asserted 26f memory access to 16-bit isa slave standard cycle 12t cycles 26h memory access to 8-bit isa slave standard cycle 12t cycles 26 ior#, iow# asserted before next ior#, iow# asserted 26i i/o access to 16-bit isa slave standard cycle 12t cycles 26k i/o access to 8-bit isa slave standard cycle 12t cycles 28 any command negated to memr#, smemr#, memr#, smemw# asserted 28a memory access to 16-bit isa slave 3t cycles 28b memory access to 8-bit isa slave 3t cycles 28 any command negated to ior#, iow# asserted 28c i/o access to isa slave 3t cycles 29a memr#, memw# negated before next ale# asserted 1t cycles 29b smemr#, smemw# negated before next ale# asserted 1t cycles 29c ior#, iow# negated before next ale# asserted 1t cycles 33 la[23:17] valid to iochrdy negated 33a memory access to 16-bit isa slave - 4 bclk 8t cycles 33b memory access to 8-bit isa slave - 7 bclk 14t cycles 34 la[23:17] valid to read data valid 34b memory access to 16-bit isa slave standard cycle 8t cycles 34e memory access to 8-bit isa slave standard cycle 14t cycles 37 ale# asserted to iochrdy# negated 37a memory access to 16-bit isa slave - 4 bclk 6t cycles 37b memory access to 8-bit isa slave - 7 bclk 12t cycles 37c i/o access to 16-bit isa slave - 4 bclk 6t cycles 37d i/o access to 8-bit isa slave - 7 bclk 12t cycles 38 ale# asserted to read data valid 38b memory access to 16-bit isa slave standard cycle 4t cycles 38e memory access to 8-bit isa slave standard cycle 10t cycles 38h i/o access to 16-bit isa slave standard cycle 4t cycles table 4-6. isa bus ac timing name parameter min max units note: the si g nal numberin g refers to table 4-12 obsolete product(s) - obsolete product(s)
electrical specifications issue 2.4 - november 8, 2001 45/71 38l i/o access to 8-bit isa slave standard cycle 10t cycles 41 sa[19:0] sbhe valid to iochrdy negated 41a memory access to 16-bit isa slave 6t cycles 41b memory access to 8-bit isa slave 12t cycles 41c i/o access to 16-bit isa slave 6t cycles 41d i/o access to 8-bit isa slave 12t cycles 42 sa[19:0] sbhe valid to read data valid 42b memory access to 16-bit isa slave standard cycle 4t cycles 42e memory access to 8-bit isa slave standard cycle 10t cycles 42h i/o access to 16-bit isa slave standard cycle 4t cycles 42l i/o access to 8-bit isa slave standard cycle 10t cycles 47 memr#, memw#, smemr#, smemw#, ior#, iow# asserted to iochrdy negated 47a memory access to 16-bit isa slave 2t cycles 47b memory access to 8-bit isa slave 5t cycles 47c i/o access to 16-bit isa slave 2t cycles 47d i/o access to 8-bit isa slave 5t cycles 48 memr#, smemr#, ior# asserted to read data valid 48b memory access to 16-bit isa slave standard cycle 2t cycles 48e memory access to 8-bit isa slave standard cycle 5t cycles 48h i/o access to 16-bit isa slave standard cycle 2t cycles 48l i/o access to 8-bit isa slave standard cycle 5t cycles 54 iochrdy asserted to read data valid 54a memory access to 16-bit isa slave 1t(r)/2t(w) cycles 54b memory access to 8-bit isa slave 1t(r)/2t(w) cycles 54c i/o access to 16-bit isa slave 1t(r)/2t(w) cycles 54d i/o access to 8-bit isa slave 1t(r)/2t(w) cycles 55a iochrdy asserted to memr#, memw#, smemr#, smemw#, ior#, iow# negated 1t cycles 55b iochry asserted to memr#, smemr# negated (refresh) 1t cycles 56 iochrdy asserted to next ale# asserted 2t cycles 57 iochrdy asserted to sa[19:0], sbhe invalid 2t cycles 58 memr#, ior#, smemr# negated to read data invalid 0t cycles 59 memr#, ior#, smemr# negated to data bus float 0t cycles 61 write data before memw# asserted 61a memory access to 16-bit isa slave 2t cycles 61b memory access to 8-bit isa slave (byte copy at end of start) 2t cycles 61 write data before smemw# asserted 61c memory access to 16-bit isa slave 2t cycles 61d memory access to 8-bit isa slave 2t cycles 61 write data valid before iow# asserted 61e i/o access to 16-bit isa slave 2t cycles 61f i/o access to 8-bit isa slave 2t cycles 64a memw# negated to write data invalid - 16-bit 1t cycles 64b memw# negated to write data invalid - 8-bit 1t cycles 64c smemw# negated to write data invalid - 16-bit 1t cycles table 4-6. isa bus ac timing name parameter min max units note: the si g nal numberin g refers to table 4-12 obsolete product(s) - obsolete product(s)
electrical specifications 46/71 issue 2.4 - november 8, 2001 4.5.6 ide interface table 4-7 lists the ac characteristics of the ide interface. 4.5.7 vga interface table 4-8 lists the ac characteristics of the vga interface. 4.5.8 video input port table 4-9 lists the ac characteristics of the vip interface. 64d smemw# negated to write data invalid - 8-bit 1t cycles 64e iow# negated to write data invalid 1t cycles 64f memw# negated to copy data float, 8-bit isa slave, odd byte by isa master 1t cycles 64g iow# negated to copy data float, 8-bit isa slave, odd byte by isa master 1t cycles table 4-6. isa bus ac timing name parameter min max units note: the si g nal numberin g refers to table 4-12 table 4-7. ide bus ac timing name parameter min max unit dd[15:0] setup to pior#/sior# falling 15 ns dd[15:0} hold to pior#/sior# falling 0 ns table 4-8. graphics adapter (vga) ac timing name parameter min max unit dclk to vsync valid 30 ns dclk to hsync valid 30 ns table 4-9. video input ac timing name parameter min max unit vin[7:0] setup to vclk 5 ns vin[7:0] hold from vclk 4 ns vclk to odd_even valid 15 ns vclk to vcs valid 15 ns odd_even setup to vclk 10 ns odd_even hold from vclk 5 ns vcs setup to vclk 10 ns vcs hold from vclk 5 ns obsolete product(s) - obsolete product(s)
electrical specifications issue 2.4 - november 8, 2001 47/71 obsolete product(s) - obsolete product(s)
electrical specifications 48/71 issue 2.4 - november 8, 2001 obsolete product(s) - obsolete product(s)
mechanical data issue 2.4 - november 8, 2001 49/71 5. mechanical data 5.1. 388-pin package dimension the pin numbering for the stpc 388-pin plastic bga package is shown in figure 5-1 . dimensions are shown in figure 5-2 , table 5-1 and figure 5-3 , table 5-2 . figure 5-1. 388-pin pbga package - top view a b d e f g h j k l m n p r t u v w y aa ab ac ad ae af c 135791113151719212325 2 4 6 8 10 12 14 16 18 20 22 24 26 a b d e f g h j k l m n p r t u v w y aa ab ac ad ae af c 135791113151719212325 2468101214161820222426 obsolete product(s) - obsolete product(s)
mechanical data 50/71 issue 2.4 - november 8, 2001 figure 5-2. 388-pin pbga package - pcb dimensions table 5-1. 388-pin pbga package - pcb dimensions symbols mm inches min typ max min typ max a 34.95 35.00 35.05 1.375 1.378 1.380 b 1.22 1.27 1.32 0.048 0.050 0.052 c 0.58 0.63 0.68 0.023 0.025 0.027 d 1.57 1.62 1.67 0.062 0.064 0.066 e 0.15 0.20 0.25 0.006 0.008 0.001 f 0.05 0.10 0.15 0.002 0.004 0.006 g 0.75 0.80 0.85 0.030 0.032 0.034 a a b detail a1 ball pad corner d f e g c obsolete product(s) - obsolete product(s)
mechanical data issue 2.4 - november 8, 2001 51/71 figure 5-3. 388-pin pbga package - dimensions table 5-2. 388-pin pbga package - dimensions symbols mm inches min typ max min typ max a 0.50 0.56 0.62 0.020 0.022 0.024 b 1.12 1.17 1.22 0.044 0.046 0.048 c 0.60 0.76 0.92 0.024 0.030 0.036 d 0.52 0.53 0.54 0.020 0.021 0.022 e 0.63 0.78 0.93 0.025 0.031 0.037 f 0.60 0.63 0.66 0.024 0.025 0.026 g 30.0 11.8 a b c solderball solderball after collapse d e f g obsolete product(s) - obsolete product(s)
mechanical data 52/71 issue 2.4 - november 8, 2001 5.2. 388-pin package thermal data the 388-pin pbga package has a power dissipation capability of 4.5w. this increases to 6w when used with a heatsink. the structure in shown in fi g ure 5-4 . thermal dissipation options are illustrated in fi g ure 5-5 and fi g ure 5-6 . figure 5-4. 388-pin pbga structure thermal balls power & ground layers signal layers figure 5-5. thermal dissipation without heatsink ambient board case junction board ambient ambient case junction board rca rjc rjb rba 66 125 8.5 rja = 13 c/w airflow = 0 board dimensions: the pbga is centred on board copper thickness: - 17m for internal layers - 34m for external layers - 10.2 cm x 12.7 cm - 4 layers (2 for signals, 1 gnd, 1vcc) there are no other devices 1 via pad per ground ball (8-mil wire) 40% copper on signal layers board temperature taken at the centrecentre b a obsolete product(s) - obsolete product(s)
mechanical data issue 2.4 - november 8, 2001 53/71 figure 5-6. thermal dissipation with heatsink board ambient case junction board ambient ambient case junction board rca rjc rjb rba 36 50 8.5 rja = 9.5 c/w airflow = 0 board dimensions: the pbga is centred on board copper thickness: - 17m for internal layers - 34m for external layers - 10.2 cm x 12.7 cm - 4 layers (2 for signals, 1 gnd, 1vcc) there are no other devices heat sink is 11.1c/w 1 via pad per ground ball (8-mil wire) 40% copper on signal layers board temperature taken at the centre balls obsolete product(s) - obsolete product(s)
mechanical data 54/71 issue 2.4 - november 8, 2001 obsolete product(s) - obsolete product(s)
design guidelines issue 2.4 - november 8, 2001 55/71 6. design guidelines 6.1 typical applications the stpc consumer is well suited for many appli- cations. some of the possible implementations are described below. 6.1.1 web box a web box is an analog set top box providing inter- net browsing capability to a tv set. it has a tv output for connecting to the tv set, a modem for internet connection, a smartcard interface for the isp access control, and an infrared interface for the remote control or the keyboard. 6.2 architecture recommendations this section describes the recommend implemen- tations for the stpc interfaces. for more details, download the "references schematics" from the stpc web site. 6.2.1 14mhz oscillator stage the 14.31818 mhz oscillator stage can be imple- mented using a quartz, which is the preferred and cheaper solution, or using an external 3.3v oscil- lator. the crystal must be used in its series-cut funda- mental mode and not in overtone mode. it must have an equivalent series resistance (esr, sometimes referred to as rm) of less than 50 ohms (typically 8 ohms) and a shunt capacitance (co) of less than 7 pf. the balance capacitors of 16 pf must be added, one connected to each pin, as described in figure 6-2 . in the event of an external oscillator providing the master clock signal to the stpc atlas device, the lvttl signal should be connected to xtalo, as described in figure 6-2 . as this clock is the reference for all the other on- chip generated clocks, it is strongly recommend- ed to shield this stage , including the 2 wires go- figure 6-1. web box stpc tv output consumer sdram 64 flash modem audio 16 pci ide / pci smartcard r,g,b, csync s-vhs cvbs vip stv2310 scart 1 scart 2 microphone infrared printer port local bus isa bus or glue logic obsolete product(s) - obsolete product(s)
design guidelines 56/71 issue 2.4 - november 8, 2001 ing to the stpc balls, in order to reduce the jitter to the minimum and reach the optimum system stability. figure 6-2. 14.31818 mhz stage 15pf 15pf xtali xtalo xtali xtalo 3.3v obsolete product(s) - obsolete product(s)
design guidelines issue 2.4 - november 8, 2001 57/71 6.2.2 pci bus the pci bus is always active and the following control signals must be pulled-up to 3.3v or 5v through 2k2 resistors even if this bus is not con- nected to an external device: frame#, trdy#, irdy#, stop#, devsel#, lock#, serr#, perr#, pci_req#[2:0]. pci_clko must be connected to pci_clki through a 10 to 33 ohms resistor. figure 6-3 shows a typical implementation. for more information on layout constraints, go to the place and route recommendations section. figure 6-3. typical pci clock routing pciclki pciclko pciclka pciclkb pciclkc 10 - 22 0 - 22 device a device b device c obsolete product(s) - obsolete product(s)
design guidelines 58/71 issue 2.4 - november 8, 2001 6.2.3 ipc most of the ipc signals are multiplexed: interrupt inputs, dma request inputs, dma acknowledge outputs. figure 6-4 describes a complete imple- mentation of the irq[15:0] time-multiplexing. when an interrupt line is used internally, the corre- sponding input can be grounded. in most of the embedded designs, only few interrupts lines are necessary and the glue logic can be simplified. when the interface is integrated into the stpc, the corresponding interrupt line can be grounded as it is connected internally. for example, if the integrated ide controller is ac- tivated, the irq[14] and irq[15] inputs can be grounded. figure 6-4. typical irq multiplexing 74x153 1c0 1y 1g irq[0] irq_mux[0] 1c1 1c2 1c3 2c0 2c1 2c2 2c3 a b 2g 2y irq_mux[1] irq[1] irq[2] irq[3] irq[4] irq[5] irq[6] irq[7] 74x153 1c0 1y 1g irq_mux[2] 1c1 1c2 1c3 2c0 2c1 2c2 2c3 a b 2g 2y irq_mux[3] irq[8] irq[9] irq[10] irq[11] irq[12] irq[13] irq[14] irq[15] isa_clk2x isa_clk timer 0 keyboard slave pic com2/com4 com1/com3 lpt2 lpt1 rtc mouse fpu pci / ide pci / ide obsolete product(s) - obsolete product(s)
design guidelines issue 2.4 - november 8, 2001 59/71 figure 6-5 describes a complete implementation of the external glue logic for dma request time- multiplexing and dma acknowledge demultiplex- ing. like for the interrupt lines, this logic can be simplified when only few dma channels are used in the application. this glue logic is not needed in local bus mode as it does not support dma transfers. figure 6-5. typical dma multiplexing and demultiplexing 74x153 1c0 1y 1g drq[0] dreq_mux[0] 1c1 1c2 1c3 2c0 2c1 2c2 2c3 a b 2g 2y dreq_mux[1] drq[1] drq[2] drq[3] drq[4] drq[5] drq[6] drq[7] 74x138 y0# a g2b dack0# y1# y2# y3# y4# y5# y6# y7# c b g2a isa_clk2x isa_clk isa, refresh isa, pio isa, fdc isa, pio slave dmac isa isa isa g1 dma_enc[0] dma_enc[1] dma_enc[2] dack1# dack2# dack3# dack5# dack6# dack7# obsolete product(s) - obsolete product(s)
design guidelines 60/71 issue 2.4 - november 8, 2001 6.2.4 vga interface the stpc integrates a vga dacs and video buff- ers. the amount of external devices is then limited to the minimum as described in the figure 6-6 . all the resistors and capacitors have to be as close as possible to the stpc while the circuit protector dalc112s1 must be close to the vga connector. the ddc[1:0] lines, not represented here, have also to be protected when they are used on the vga connector. col_sel can be used when implementing the picture-in-picture function outside the stpc, for example when multiplexing an analog video source. in that case, the crtc of the stpc has to be genlocked to this analog source. dclk is usually used by the tft displays which have rgb inputs in order to synchronise the pic- ture at the level of the pixel. when the vga interface is not needed, the signals r, g, b, hsync, vsync, comp, rset can be left unconnected, vss_dac[2:1] and vdd_dac must then be connected to gnd. 6.3 place and route recommendations figure 6-6. typical vga implementation 536 vdd_dac comp vref_dac rset vss_dac1 3.3v 10nf 100nf 47uf agnd col_sel dclk hsync vsync r g b 75 1% dalc112s1 agnd 3.3v vss_dac2 1% 100nf 1k 16vlm385bz obsolete product(s) - obsolete product(s)
design guidelines issue 2.4 - november 8, 2001 61/71 6.3.1 general recommendations some stpc interfaces run at high speed and need to be carefully routed or even shielded like: 1) memory interface 2) pci bus 3) graphics and video interfaces 4) 14 mhz oscillator stage all clock signals have to be routed first and shield- ed for speeds of 27mhz or higher. the high speed signals follow the same constraints, as for the memory and pci control signals. the next interfaces to be routed are memory, pci, and video/graphics. all the analog noise-sensitive signals have to be routed in a separate area and hence can be rout- ed indepedently. figure 6-7. shielding signals ground ring ground pad shielded signal line ground pad shielded signal lines obsolete product(s) - obsolete product(s)
design guidelines 62/71 issue 2.4 - november 8, 2001 6.3.2 thermal dissipation 6.3.2.1 power saving thermal dissipation of the stpc depends mainly on supply voltage. when the system does not need to work at the upper voltage limit, it may therefore be beneficial to reduce the voltage to the lower voltage limit, where possible. this could save a few 100s of mw. the second area to look at is unused interfaces and functions. depending on the application, some input signals can be grounded, and some blocks not powered or shutdown. clock speed dy- namic adjustment is also a solution that can be used along with the integrated power manage- ment unit. 6.3.2.2 thermal balls the standard way to route thermal balls to ground layer implements only one via pad for each ball pad, connected using a 8-mil wire. with such configuration the plastic bga package does 90% of the thermal dissipation through the ground balls, and especially the central thermal balls which are directly connected to the die. the remaining 10% is dissipated through the case. adding a heat sink reduces this value to 85%. as a result, some basic rules must be followed when routing the stpc in order to avoid thermal problems. as the whole ground layer acts as a heat sink, the ground balls must be directly connected to it, as il- lustrated in figure 6-8 . if one ground layer is not enough, a second ground plane may be added. figure 6-8. ground routing pad for ground ball thru hole to ground layer t o p l a y e r : s i g n a l s p o w e r l a y e r i n t e r n a l l a y e r : s i g n a l s b o t t o m l a y e r : g r o u n d l a y e r note: for better visibility, ground balls are not all routed. obsolete product(s) - obsolete product(s)
design guidelines issue 2.4 - november 8, 2001 63/71 when considering thermal dissipation, one of the most important parts of the layout is the connec- tion between the ground balls and the ground lay- er. a 1-wire connection is shown in figure 6-9 . the use of a 8-mil wire results in a thermal resistance of 105c/w assuming copper is used (418 w/ m.k). this high value is due to the thickness (34 m) of the copper on the external side of the pcb. considering only the central matrix of 36 thermal balls and one via for each ball, the global thermal resistance is 2.9c/w. this can be easily im- proved using four 12.5 mil wires to connect to the four vias around the ground pad link as in figure 6-10 . this gives a total of 49 vias and a global re- sistance for the 36 thermal balls of 0.5c/w. the use of a ground plane like in figure 6-11 is even better. figure 6-9. recommended 1-wire power/ground pad layout solder mask (4 mil) pad for ground ball (diameter = 25 mil) hole to ground layer (diameter = 12 mil) connection wire (width = 12.5 mil) via (diameter = 24 mil) 34.5 mil 1 mil = 0.0254 mm figure 6-10. recommended 4-wire ground pad layout 4 via pads for each ground ball obsolete product(s) - obsolete product(s)
design guidelines 64/71 issue 2.4 - november 8, 2001 to avoid solder wicking over to the via pads during soldering, it is important to have a solder mask of 4 mil around the pad (nsmd pad). this gives a di- ameter of 33 mil for a 25 mil ground pad. to obtain the optimum ground layout, place the vias directly under the ball pads. in this case no lo- cal board distortion is tolerated. 6.3.2.3 heat dissipation the thickness of the copper on pcb layers is typ- ically 34 m for external layers and 17 m for inter- nal layers. this means that thermal dissipation is not good; high board temperatures are concen- trated around the devices and these fall quickly with increased distance. where possible, place a metal layer inside the pcb; this improves dramatically the spread of heat and hence the thermal dissipation of the board. the possibility of using the whole system box for thermal dissipation is very useful in cases of high internal temperatures and low outside tempera- tures. bottom side of the pbga should be ther- mally connected to the metal chassis in order to propagate the heat flow through the metal. ther- mally connecting also the top side will improve fur- thermore the heat dissipation. figure 6-12 illus- trates such an implementation. figure 6-11. optimum layout for central ground ball - top layer via to ground layer pad for ground ball clearance = 6mil diameter = 25 mil hole diameter = 14 mil solder mask diameter = 33 mil external diameter = 37 mil connections = 10 mil figure 6-12. use of metal plate for thermal dissipation metal planes thermal conductor board die obsolete product(s) - obsolete product(s)
design guidelines issue 2.4 - november 8, 2001 65/71 as the pcb acts as a heat sink, the layout of top and ground layers must be done with care to max- imize the board surface dissipating the heat. the only limitation is the risk of losing routing chan- nels. figure 6-13 and figure 6-14 show a partial routing with a good thermal dissipation thanks to an optimized placement of power and signal vias. the ground plane should be on bottom layer for the best heat spreading (thicker layer than internal ones) and dissipation (direct contact with air). . figure 6-13. layout for good thermal dissipation - top layer 1 a not connectedball via stpc ball gnd ball obsolete product(s) - obsolete product(s)
design guidelines 66/71 issue 2.4 - november 8, 2001 figure 6-14. recommend signal wiring (top & ground layers) with corresponding heat flow stpc balls external row internal row gnd power power obsolete product(s) - obsolete product(s)
design guidelines issue 2.4 - november 8, 2001 67/71 obsolete product(s) - obsolete product(s)
design guidelines 68/71 issue 2.4 - november 8, 2001 obsolete product(s) - obsolete product(s)
ordering data issue 2.4 - november 8, 2001 69/71 7. ordering data 7.1 ordering codes st pc c01 66 bt c 3 stmicroelectronics prefix product family pc: pc compatible product id c01: consumer core speed 66: 66mhz 75: 75mhz 80: 80mhz 10: 100mhz package bt: 388 overmoulded bga temperature range c: commercial 0 to +70c tcase = 0 to +100c i: industrial -40 to +85c tcase = -40 to +100c operating voltage 3 : 3.3v 0.3v obsolete product(s) - obsolete product(s)
ordering data 70/71 issue 2.4 - november 8, 2001 7.2 available part numbers part number core frequency (mhz) cpu mode tcase range (c) operating voltage (v) stpcc0166btc3 66 dx 0c to +100c 3.3v 0.3v stpcc0180btc3 80 dx stpcc0166bti3 66 dx -40c to +100c stPCC0180BTI3 80 dx obsolete product(s) - obsolete product(s)
information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. ? 2000 stmicroelectronics - all rights reserved the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. stmicroelectronics group of companies australia - brazil - china - france - germany - italy - japan - korea - malaysia - malta - mexico - morocco - the netherlands - singapore - spain - sweden - switzerland - taiwan - thailand - united kingdom - u.s.a. 97 issue 2.4 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change wit hout notice. obsolete product(s) - obsolete product(s)

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